By Jim Nesbitt
In the mid 1960’s the Integrated Circuit, Monolithic, Hybrid Operations began in the Building 50 Tech Center on the 3rd floor. There was a small horizontal-flow, class 100 clean room near the SW corner. This contained all the production tools to produce ICs at the time except for Mask Making, Test, and Packaging operations. Later this and the Packaging operation expanded to occupy 3/4 of the 3rd floor.
At some point Building 48 was completed to contain the Manufacturing Division, while Building 50 continued as the Engineering Division – hence the skybridge between Buildings 48 and 50. Then around 1980, Building 59 was completed and the entire IC production, including Mask Making moved there. Hybrids went to Building 13. CMOS/CCD operations remained in Building 48 for some time before joining operations at Building 59.
The Building 50 Mask Making Operation was located partially on the second floor with the gigantic camera in the basement. The camera took images of the IC Chips architecture to be shrunk from many yards to a couple of millimeters, being transferred to glass slides about 3” square that were then placed in an aligner to have the image burned into a photoresist coating on a silicon wafer. At first the wafers were an inch in diameter gradually gaining size to 3-inch. By comparison, most wafer fabs today use 450mm (18”) or larger wafers. It’s important to note here that silicon is the crystalline substrate wafer material, whereas silicone is used for sealing up leaky windows.
In the early Tek clean room on the third floor of Building 50 there were two Kasper Aligners where a wafer with photo resist would be guided along a belt or air float path onto a platen where it was held fast with vacuum once properly oriented. A glass mask was already in place. The operator would lower the microscope and mask until the mask was a few microns above the wafer, the operator would work two paddles one in each hand slowly guiding the mask around until a perfect match was achieved aligning with the image already on the wafer (unless this was a first layer) then they would push a button vacuum sealing the mask to the wafer, and pushing another button to move the shutter away from a very high intensity ultraviolet lamp exposing the photoresist for the prescribed time. The vacuum would release, the wafer would transport to a waiting cassette, repeating until the supply cassette was empty. In some cases, the operator of the aligner was able to use “proximity mode” leaving a micron or so gap between the mask and wafer.
In today’s world there is no longer a mask, rather a direct projection of the image to the wafer. In fact, Chief Engineer Doug Ritchie was bringing on very expensive Canon Projection Aligners even while the old Kasper aligners were in everyday use.
It should be pointed out here that the reason these operations are done in a clean room is because if a half micron particle were to land on the photo resist it would be smashed by the pressing together of the mask and wafer with high vacuum, which in turn could wipe out or short the half to one-micron wide traces on the wafer. Yields were always a problem, since the clean room has a bank, floor to ceiling, of wall-to-wall HEPA filters at the cleanest end of the clean room, which at the time was a federal class 100 which translated to <100 0.5µm particles per cubic foot of air. The air in a horizontal flow cleanroom flows at ~90 fpm, therefore any wafer or mask is subject to a snowstorm of particulate. Frankly it’s a miracle that any of those early wafers produced any useable product.
Today’s cleanrooms use so-called absolute air filters, where the particle counts are less than 1each at 0.3 µm per cu. ft. The air flows downward from an entire ceiling of absolute air filters and returns thru a raised floor of perforated tiles. And of course, so-called bunny suits of very low particulate generation are worn as well as booties and nitrile gloves. The wafers are seldom if ever exposed, travelling in air tight boxes on automated tracks from one station to the next. Back in the day this was called the “Smiph System”.
While in Building 50, ICs were being developed around 0.5µm line width technology under chief engineer Doug Ritchie. Consider that in the present-day Taiwan Semiconductor is routinely producing 0.7 nm line widths, a dimension reduction of three orders of magnitude, or 1,000 times.
Once a batch of wafers has gone thru all the other steps, which generally takes months, it goes to Test to see how many actual useable chips, or die, are on the wafer. The bad ones are marked and then the wafer is sawed with an extremely thin diamond blade along all the scribe lines. The individual die are then sent to packaging where employees with extreme talent bonded micro-sized gold wire to the individual contact points on a chip only a couple of mm square. The number of contacts can be anywhere from eight to dozens. The chip with the attached metal lattice is then molded in the familiar eight-legged caterpillar configuration.
The CCD/CMOS operations moved into the vacated Engineering Development fab/Lab in Building 59, producing their normal CCD/CMOS devices and “backside imagers” under a very secret, proprietary process. The CCD used in the first Hubble Imager was produced here. The shipping container cost $10,000 and was shipped with very detailed instructions on how to open this device and how to prevent destruction of the device once out of the package. The imager was very susceptible to fields of static electricity. Unfortunately, the receiving engineer for the Hubble operation ignored all those instructions, thereby instantly destroying the imager, proclaiming that Tektronix had shipped a defective product forcing Tek to manufacture and send another one.
On May 30th 1994 Building 59 and the entire Integrated Circuit Operation was sold to Maxim Integrated Products. TriQuint, CCD/CMO were not included in the sale and continued to lease space from Maxim. Eventually, TriQuint spun off under a different name, “Qorvo”, moving to Hillsboro, Oregon. CMOS/CCD operations continued for a while before leasing space elsewhere.
TriQuint made use of very specialized semiconductor production, employing gallium arsenide wafers. Gallium and arsenic come from columns three and five, respectively, in the Periodic Table of the Elements. Gallium arsenide is therefore sometimes referred to as a “three-five” material, hence the name Tri-Quint. The resulting chips are used for high frequency applications, such as satellite communications.
Sidenote: When Building 59 was nearing completion in 1980, it was declared the most expensive building in the state of Oregon at $100,000,000+ not counting tooling. The building incorporated ridiculous overkill, over fears of what vibrations may occur from occasional passing trains on a track nearly a mile away. The building rests on gigantic blocks of what appears to be Styrofoam. The second-floor hall ways are suspended on coil springs. (after about 10 years the springs were permanently compressed to stop the disconcerting movement of the hallways underfoot). The building was sold to Maxim in 1994.
What I do appreciate though is the 33 years spent at Tektronix, before Maxim, where I was able to achieve what I never dreamed possible. It was such a great place to work that many past workers are dedicated to the vintageTEK Museum where all those fond memories are stored.